Interconnection Length Estimation During Hierarchical VLSI Design
نویسندگان
چکیده
A lognormal interconnection length distribution function is derived from a large number of VLSI layouts. The assumption of a Weibull distribution could not be confirmed. Hierarchical slicing trees are derived from structural descriptions of the sample systems by recursive partitioning. Using the earlier proposed area estimation results, a new model for interconnection length estimation based on slicing trees is proposed, also resulting in a lognormal length distribution with parameters close to the layout results. We therefore believe that the results are a step forward towards understanding and predicting interconnection lengths and logical path delays before layout.
منابع مشابه
Fuzzy logic approach to VLSI placement
-A contemporary definition of VLSI placement problem is characterized by multiple objectives. These objectives are: timing, chip area, interconnection length and possibly others. In this paper, fuzzy logic has been used to facilitate multiobjective decision-making in placement for standard cell design style. A placement process has been defined in terms of linguistic variables, linguistic value...
متن کاملAn Accurate Interconnection Length Estimation for Computer Logic
Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths [2]. Yet, this upper bound deviates from the experi...
متن کاملOn the Characterization of Multi-Point Nets in Electronic Designs
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those properties is essential for improving placement and routing techniques for digital circuits. Previous work on estimating design properties failed to take multi-point nets into account. All nets were assumed to be 2-point n...
متن کاملMultilayer VLSI Layout for Interconnection Networks
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-layer model, the layout area for a variety of networks can be reduced by a factor of about L 2 2 compared to the layout area required under a 2-layer model, and the volume and maximum wire length can be reduced by a fac...
متن کاملPerformance Analysis of VLSI Floor planning using Evolutionary Algorithm
Floorplanning is an important physical design step for hierarchical, building-block design methodology. When the circuit size get increases the complexity of the circuit also increases. To deal with the increasing design complexity the intellectual property (IP) modules are mostly used in floorplanning. This paper presents a Hybrid particle swarm optimization algorithm for floorplanning optimiz...
متن کامل